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jishuqi.rar
- 描述的是一个带有异步复位和同步时钟使能的十进制加法计算器,,With reset and clock enable decimal calculator
clock.rar
- VHDL编写的,实现电子手表功能,硬件语言描写,定时非常准确,VHDL prepared, electronic watches, functions, hardware descr iption languages, timing is very accurate
zz.rar
- 键控加/减计数器,将20MHz系统时钟经分频器后可得到5M、1M、100K、10K、5K、1K、10Hz、1Hz ,Keying increase/decrease counter to 20MHz system clock by the divider available after 5M, 1M, 100K, 10K, 5K, 1K, 10Hz, 1Hz
baseband_verilog.rar
- verilog实现的基带信号编码,整个系统分为六个模块,分别为:时钟模块,待发射模块,卷积模块,扩频模块,极性变换和内插模块,成型滤波器,verilog implementation baseband signal coding, the entire system is divided into six modules, namely: the clock module, to be launched modules, convolution module, spread spectrum m
FPGA-digital-clock-design
- 运用顶层设计思路设计好各个底层文件(VHDL代码),对各个底层文件进行功能仿真;采用原理图或者文本方法来实现顶层文件的设计,对顶层文件进行功能真仿真。在顶层文件功能仿真正确之后,把顶层文件下载到实验箱的FPGA里边去,验证电路功能是否正确。具体时间用6位数码管来显示,具有整点报时功能. -Designed various underlying file using top level design (VHDL code), on functional simulation of variou
music
- 设计并调试好一个能产生”梁祝”曲子的音乐发生器,并用EDA实验开发系统(拟采用的实验芯片的型号可选Altera的MAX7000系列的 EPM7128 CPLD ,FLEX10K系列的EPF10K10LC84-3 FPGA, ACEX1K系列的 EP1K30 FPGA,Xinlinx 的XC9500系列的XC95108 CPLD,Lattice的ispLSI1000系列的1032E CPLD)进行硬件验证。 设计思路 根据系统提供的时钟源引入一个12MHZ时钟的基准频率,对其进行各种分频
RX
- 1路视频光端机的接收端,VHDL源码,使用全FPGA芯片的硬件,内建解帧、时钟、DESERDES-PDH a video of the receiving end, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
dpll
- dpll的verilog代码,完成数字锁相。用于时钟对准,位同步。-dpll the verilog code to complete the digital phase-locked. Alignment for the clock, bit synchronization.
part2
- Implement a 3-digit BCD counter. Display the contents of the counter on the 7-segment displays, HEX2− 0. Derive a control signal, from the 50-MHz clock signal provided on the DE2 board, to increment the contents of the counter at one-se
DS1302
- 基于VerilogHDL编写的时钟管理芯片DS1302实验开发程序。-VerilogHDL prepared based on clock management chips DS1302 experimental development program.
clock
- 万年历与电子时钟的VHDL程序设计,万年历与电子时钟的VHDL程序设计-clock
TX
- 1路视频光端机的发射端,VHDL源码,使用全FPGA芯片的硬件,内建成帧、时钟、SERDES-The launch of a video PDH client, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
SDH
- SDH开销的接收处理,要求: 1, A1和A2字节为帧头指示字节,A1为“11110110”,A2为“00101000”,连续3个A1字节后跟连续3个A2字节表示SDH一帧的开始。要求自行设计状态机,从连续传输的SDH字节流中找出帧头。 2, E2字节为勤务话通道开销,用于公务联络语音通道,其比特串行速率为64KHz(8*8K=64)。要求从SDH字节流中,提取E2字节,并按照64K速率分别串行输出E2码流及时钟,其中64K时钟要求基本均匀。(输出端口包括串行数据和64K串行时钟)
50M
- verilog 语言写的分频模块,实现用50Mhz的时钟频率分出1hz的频率,也就是一秒的频率-verilog language sub-frequency module, using the 50Mhz clock frequency 1hz separation, that is, the frequency of second
DCM
- ISE实现DCM组建例化,得到3倍频时钟-ISE to achieve established cases of DCM, received 3 octave clock
rs232
- fpga的串口读写程序,经硬件测试成功,波特率9600.可以改变分频值适应不同的时钟和波特率-fpga serial read and write procedures, by the hardware to test the success of 9600 baud rate. frequency value can be changed to adapt to a different clock and baud rate
1234
- 多功能数字钟,、在quartus 2环境中编译通过; 4、仿真通过并得到正确的波形; 5、给出相应的设计报告 -Multifunction digital clock, in the quartus 2 compiler environment through 4, simulation through and get the correct waveform 5, gives the design report
clk_vhdl
- Quartus II工程压缩文件,是一个典型的基于FPGA的数字钟工程项目,有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based digital clock project, there are sub-50MHz frequency, counting, decoding modules. Using VHDL language.
oc_mkjpeg
- Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design document. Written in VHDL. Verified on Xilinx XC4VLX25. Rncode 320x240 bmp picture in 3ms at 50 quality, 100Mhz clock.-Pure hardware JPEG Encoder design.
serial
- -- 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在 --PC机上安装一个串口调试工具来验证程序的功能。 -- 程序实现了一个收发一帧10个bit(即无奇偶校验位)的串口控 --制器,10个bit是1位起始位,8个数据位,1个结束 --位。串口的波特律由程序中定义的div_par参数决定,更改该参数可以实 --现相应的波特率。程序当前设定的div_par 的值是0x104,对应的波特率是 --9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时